1. Field of the Invention
This invention relates to a read-only memory device adapted for reading out data programmed in a memory cell and, more particularly, to a read-only memory device having NOR type memory cells.
2. Description of the Prior Art
With the read-only memory device (ROMs) adapted for storing a large amount of data and reading out the stored data when necessary, a demand for a higher degree of integration has been raised in keeping pace with propagation of OA equipment or electric computers.
As a typical structure for realizing such high integration, there is known a mask ROM having a NAND type cell circuit construction which has a so-called multi-gate structure provided with a gate electrode layer formed by two polysilicon layers, and a shallow groove or trench, as disclosed for example in "8M and 16M mask ROM Employing Shallow Trench" in a monthly magazine entitled "Semiconductor World", October, 1987, pages 33 to 38. On the other hand, there is known a mask ROM having a NOR type cell circuit construction which has its source-drain region constructed by a diffusion region, as disclosed for example in "16 Mb ROM Design Using Bank Select Architecture" in 1988 Symposium on VLSL circuits, Japan Association of Applied Physics, material, VL-7, pages 85 to 86.
FIG. 1 is a circuit diagram showing essential portions of the mask ROM having the NOR type memory cells. With this mask ROM, each of the memory cells 200 arranged in a matrix configuration and adapted to be selected by word lines W.sub.1 to W.sub.8 is constituted by each one MOS transistor, the source-drain region of which is formed by a diffusion region which proves to be common bit lines 205, 206 and 207 for each column. With this mask ROM, virtual grounding lines 201 and main bit lines 202 are formed alternately, with the direction normal to the extending direction of the word lines as the longitudinal direction. These virtual grounding lines 201 and the main bit lines 202 are wired with a shift of one bit line one so as to be connected to different columns for one and the other of memory cell blocks. Thus the same bit line may be connected to the virtual grounding line 201 or to the main bit line 202 by alternative selection or bank selection of selection transistors 203 and 204. For readout, a given column is selected by column selection transistor 208 and a word line is selected so that data may be read out by means of the main bit line 202 and sense amplifier 209 and transmitted to an output terminal.
In FIG. 2, which shows the layout of the mask ROM shown in FIG. 1, the region indicated by numerous dots indicates polysilicon layers which are arrayed parallel to one another with the X-direction as the longitudinal direction. The region sandwitched between a pair of contact holes 211, 211 in the Y-direction represents a memory block. A diffusion region 213 where the contact hole 211 is formed is roughly of a pattern in the form of a letter H. Diffusion regions 205 to 207, . . . indicate bit lines functioning as the source-drain region. The channel of the transistor of each cell is formed in the lower portions of the word lines W.sub.1 to W.sub.8. Programming in performed by introducing impurities into the channel with the use of a mask pattern 212. Gate electrodes SO.sub.i, SO.sub.i+1 of a selection transistor 204 and gate electrodes SE.sub.i, SE.sub.i+1 of a selection transistor 203 used for bank selection are extended parallel to the word lines W.sub.1 to W.sub.8, and are arranged on both sides of the memory block.
With the above described NAND type cell, the memory cell driving capability is lowered when the number of serially connected transistors is increased with a view to achieving a higher degree of integration.
On the other hand, with the NOR type cell mask ROM, the following layout problems are raised.
The transistor channel of each cell is formed at the lower portion of the word lines W.sub.1 to W.sub.8, with the channel direction being the X-direction. However, with the selection transistors 203, 204 for bank selection, the channel region is formed between the bit lines 205 to 207, . . . and the substantially H-shaped diffusion region 213, despite the fact that the gate electrodes SE.sub.i, SE.sub.i-1, SO.sub.i and SO.sub.i+1 thereof run parallel to word lines W.sub.1 to W.sub.8. Thus the channel direction of these selection transistors is the Y-direction. Therefore, with the selection transistors 203, 204 for bank selection, the channel stop region need to be formed between the adjoining channels in the lower portions of the gate electrodes SE.sub.i, SE.sub.i-1, SO.sub.i and SO.sub.i+1. Thus, while it suffices in the memory cell region to perform channel stop ion implantation in alignment with word lines W.sub.1 to W.sub.8, it is necessary to perform ion implantation separately from that for the memory cell region. Since the channel stop region cannot be formed in alignment with the polysilicon layer, it is necessary to provide a margin to take account of mask deviation. The necessity for providing such a margin results in limitations on the memory block side region and consequent difficulties in improving the degree of integration of the memory device.